Solid state memories (SSMs) often comprise one or more arrays of individually programmable memory cells configured to store data by the application of write currents to the cells to store a sequence of bits. The stored bits can be subsequently read during a read operation by applying suitable read currents and sensing voltage drops across the cells.
Some SSM cell configurations employ a logical storage bit coupled to a switching device. The resistive element can be programmed to different resistances to represent different bit states while the switching device allows selective access to the resistive sense element during read and write operations.
A continued trend is to provide SSM arrays with larger data capacities and smaller manufacturing process feature sizes. However, the physical requirements of many switching devices have made implementation of such components more difficult. Furthermore, smaller feature sizes can pose a high potential for errors when reading and writing data due to close proximity to other components and high programming current often used in modern logical storage bits.
As such, there is a continued need for improved non-volatile memory cells, specifically with respect to reducing the physical overhead of switching devices while reducing operational data access errors.